Job Description

About the job Analog Engineer | Digital Engineer | IC Designer

About the Company

\xef\xbb\xbf\xef\xbb\xbfOur client is a public listed company on Mainboard of Bursa Malaysia. Our client specializes in design and manufacturing of IoT chips and system, connecting any electronics and non-electronic items to the Internet.

Job Responsibilities

• \xef\xbb\xbfLead the PHY architecture development for PCIe 5.0 and USB4 standards
• Defines, Documents and Designs of PHY Architectures
• System modeling of PHY with Verilog
• System integration of PHY with controller
• Hands-On Experience in high-speed design building blocks for High-Speed Interfaces, SERDES, PLL, CDR, RTL logic design, Synthesis, Physical design, Power analysis and/or integration aspects for IO PHY in SoC
• Taped-out in PHY Finfet process
• PHY Architecture knowledge needs to span multiple domains (Analog, Digital, Platform Electricals, etc.)
• Cross-discipline knowledge in any of these areas, such as Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid and

Architecture specification documentation. * Innovate and own System Modeling, Architecture, Design and Development of high performance, low power IO PHY meeting latest USB4 and PCIe 5.0

• Owns PHY level Architecture study and recommends system level design trade-off aligned to IP/SoC requirement and roadmap
• Collaborate across functional teams - Logic, Circuit, Verification, Structural Design in PHY level definition meeting Best in Class Power, Performance and Area metrics
• Collaborate with SoC integration teams on PHY level requirement and integration issues Mentor and develop technical leadership\xef\xbb\xbf

Consultant in charge

\xef\xbb\xbfJia En | 016 266 2236 |

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