Participate in block/IP/chip floor planning from scratch, performing routing & layout verification (such as LVS, DRC, Antenna & others) and troubleshooting the results
Co-lead/lead the physical layout of IP/full chip design by working closely with cross functional team leader
Conduct thorough layout design reviews internally & external review with circuit designers
Extensive use of CAD tools (
Cadence Virtuoso--VXL & Mentor Calibre
) in IP/chip integration and verification
Capable in guiding/coaching junior engineers for on time delivery & quality
Job Requirements:
Bachelor's degree in electrical/Electronic Engineering/Physics with VLSI exposure or equivalent at least 6 years of job experience in layout design field is preferred.
Hands-on experience in
analog layout from scratch, implementation of analog layout techniques, IR drop/EM analysis
Deep understanding of analog circuit layout concepts in submicron CMOS technologies
Job Types: Full-time, Permanent
Pay: RM7,000.00 - RM13,000.00 per month
Benefits:
Health insurance
Opportunities for promotion
Professional development
Experience:
analog layout design: 5 years (Required)
Work Location: In person
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