Job Description

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RTL coding and module-level verification of digital IC circuit blocks Assist DV engineering team for system-level verification and debug Assist in creating and maintaining design documentation Assist in the completion of sign-off GDSII working with DFT and PD engineering teams.

Requirement -

Highly motivated and driven to solve challenging design problems Able to read and understand the architectural specifications at the sub-system/chip level Comprehend the Power-Performance-Area trade-offs in the development of micro-architecture Proficient with at least one programming language

Preferred experience -

Concentration/major in IC Design Hands-on experience in digital IC design Knowledge of industry Protocols - PCIe, NVMe, USB4.0, DDR, AXI, CHI, AHB, MIPI, Display port, Ethernet etc. Design Techniques - Low-power, UPF, Clock Domain Crossing (CDC), Booting/Reset Flow Proficient in a scripting languages - Shell scripting, Python, Tcl, PERL etc.
Job Type: Full-time

Pay: RM3,500.00 - RM5,000.00 per month

Benefits:

Flexible schedule Health insurance
Application Question(s):

What are the key differences between blocking (=) and non-blocking (<=) assignments in Verilog/SystemVerilog, and when must you use each type to ensure a correct, synthesizable design? Design a Finite State Machine (FSM) in Verilog that detects the overlapping serial sequence "101" at its input, and describe the trade-offs between a Mealy and Moore machine implementation for this problem.
Work Location: In person