Job Description

Seeking a Senior Staff Analog Layout Engineer (RF Layout) to lead and execute complex RF/analog layout designs, guide junior engineers, and collaborate cross-functionally to ensure high-performance circuit delivery.
Key Responsibilities:
Collaborate with RF designers to optimize and iterate circuit layouts.
Perform critical circuit block, subsystem, and top-level layout using Cadence Virtuoso VXL & Mentor Calibre and advanced RF node processes.
Plan and execute RF floor planning, routing, and DRC/LVS verification.
Lead/co-lead RF IP layout and ensure design quality through reviews.
Coordinate with cross-functional teams for layout integration.
Conduct internal and external design reviews.
Manage project schedules and assign tasks within the layout team.
Mentor and coach junior engineers for quality and timely delivery.
Required Skills:
8 to 15 years of hands-on RF/analog layout experience (especially from scratch).
Proficient in Cadence Virtuoso VXL & Mentor Calibre.
Strong knowledge in high-frequency RF blocks (LNA, Mixer, PA, VCO, PLL).
Deep understanding of submicron CMOS analog layout concepts.
Skilled in parasitic reduction, matching, ESD, and DFM techniques.
Experience in layout verification (LVS, DRC).
Strong analytical, problem-solving, and productivity improvement focus.
Excellent communication and team collaboration skills.
Additional Info:
Bachelor's degree in EE/ECE/Physics with VLSI exposure preferred.
Prior experience in WLAN/BT chip layout design is an advantage.