Mask Design Engineer @ PENANG *Multiple headcounts available / Hybrid / Senior to above Senior Staff / Permanent* VLSI component layout and translation of schematics into layout geometry Participate in module/chip floor planning , perform layout verification (such as LVS, DRC, Antenna & others), and troubleshoot the results. Extensive use of CAD tools ( Cadence Virtuoso--VXL & Calibre ) in chip assembly and verification Perform block level/full chip verification check and fixes Education- Physics with VLSI exposure or equivalent Job experience in the layout design field is preferred. Knowledge of VLSI Layout Design, IO Layout Design, and geometrical design rules will be an added advantage.
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