1. Architecture definition and schematic design of RAM and ROM compilers to get the most optimal circuit in terms of power and performance.
2. Verification of leaf cells/circuit blocks including analysis of circuit behavior, timing marginalities, correct description of timing characterization intent on both pre and post layout netlist across the entire PVT space and compiler cut space.
3. Implement memory characterization flows based on NLDM/NLPM and CCS characterization
4. Mitigate risks through proactive design analysis
5. Generate front-end views (LIB) for memory IP integration in System-on-Chip.
6. Documentation and design review organization for compliant development in the context of ISO26262
7. Development QA flow for design verification
8. Any other assignment and role deemed appropriated might be assigned to you from time to time
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