Rtl Design Engineer

Pulau Pinang, Malaysia

Job Description


Performing concept studies and provide direction in terms of performance, gate count and power for various digital designs. Writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. Providing high-quality RTL description, including assertions, for the design. Formal tools and static checkers will be used to guarantee RTL quality. Supporting design verification to insure bug-free first silicon. Driving functional and code coverage as well as timing closure for your designs. Supporting silicon bring-up, performance and power characterization Skills Required: RTL design using Verilog or System Verilog, assertion writing Design of state machines, data paths, arbitration and clock domain crossing logic Logic synthesis, timing constraints Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking Prior experience in DDR PHY design and mixed-signal environment is a plus Minimum have 4 year working experience

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Job Detail

  • Job Id
    JD940033
  • Industry
    Not mentioned
  • Total Positions
    1
  • Job Type:
    Full Time
  • Salary:
    Not mentioned
  • Employment Status
    Permanent
  • Job Location
    Pulau Pinang, Malaysia
  • Education
    Not mentioned