Senior Engineer Design Verification

Malaysia, Malaysia

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Job Requirements

3-10 Yrs of Subsystem Level Verification.
Test Plan Writing, Knowledgeable in UVM and System Verilog, Debugging RTL issues, Coverage Writing and SVA Waveform debug using Verdi.
Knowledgeable in USB waveform is a plus.
MUST have more than 5 years of DV experience.
MUST work in Penang, Malaysia

Work Experience

3-10 Yrs of Subsystem Level Verification.
Test Plan Writing, Knowledgeable in UVM and System Verilog, Debugging RTL issues, Coverage Writing and SVA Waveform debug using Verdi.
Knowledgeable in USB waveform is a plus.
MUST have more than 5 years of DV experience.
MUST work in Penang, Malaysia

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