Senior Engineer, Ip Design
Pulau Pinang, Malaysia
Job Description
Lattice Overview
We are seeking a Senior IP Design Engineer with significant hands-on experience in FPGA RTL design, logic simulation, FPGA compilation and timing closure and hardware debug.
Responsibilities & Skills
Requirements:
Key Skills:
- Hands-on experience in FPGA RTL design, logic verification, debug and timing closure
- Programming skills (e.g.: C/C++, Perl, TCL or Python)
- Experience in DDR protocols
- Experience in hardware validation and debug is a plus
- Experience in soft IP packaging, example design and testbench development will be an added advantage
- BS/MS/PhD in Electronics or Computer Engineering minimum of 5-7 years of FPGA system design experience
- Independent and self-motivated, capable of executing under dynamic environment and uncertainties
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Job Detail
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Job IdJD984973
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IndustryNot mentioned
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Total Positions1
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Job Type:Full Time
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Salary:Not mentioned
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Employment StatusPermanent
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Job LocationPulau Pinang, Malaysia
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EducationNot mentioned