Job Summary:
We are looking for a Memory Design Engineer to contribute to a highly innovative team by designing and developing high quality SRAM and ROM. You will work with other team members on the new process design challenges. You will have the chance to create novel low power and high-performance circuits and develop in-house design and verification flows for SRAM and ROM design in the context of ISO26262.
As a part of SRAM/ROM Design team, you would be working on
Architecture definition and schematic design of RAM and ROM compilers to get the most optimal circuit in terms of power and performance.
Verification of leafcells/circuit blocks including analysis of circuit behavior, timing marginalities, correct description of timing characterization intent on both pre and post layout netlist across the entire PVT space and compiler cut space.
Implement memory characterization flows based on NLDM/NLPM and CCS characterization
Mitigate risks through proactive design analysis
Generate front-end views (LIB) for memory IP integration in System-on-Chip.
Documentation and design review organization for compliant development in the context of ISO26262
Development QA flow for design verification including EMIR analysis
Job requirements
Qualification: Master or higher in Electronics Engineering.
Minimum 5 years of working experience in memory schematic design and characterization. Exposure to complete design cycle of SRAM/ROM memory development
Skills/Competencies:
Behavioral Competencies
Good communication skills ? good level in English, written and spoken.
Teamwork and collaboration skills, working within multi-national, multi-site team
Open, curious in new design implementation, integrity and friendly when engaging internal/external customers.
Self-motivated, progressive attitude, and able to work independently with minimum supervision
Excellent writing and reporting skills with strong communication and analytical skills
Able to learn quickly, self-driven and results-oriented
Technical/ Functional Competencies
Experience in using EDA tools for schematic entry and advanced transistor level simulators. Proven experience on transistor-level circuit design and circuit behavior analysis
Solid understanding of device physics and process
Knowledge of industry standard circuit simulation and design tools
Deep background of the design, verification, and characterization of SRAM/ROM
Solid understanding on generating performance/power/margin data of SRAM/ROM, validation of data and QA process
Knowledge of EMIR and their impacts to circuit/layout implementations and signoff flows would be an advantage
Hands-on experience running SPICE simulation, and capability to adapt to new simulation tools
Experience in Programming language, such as, Perl, Python, Tcl, and automation methods/algorithms is an advantage
In-depth understanding of circuit fundamentals with a good exposure to digital and analog circuit design is a must. Strong experience to Memory design and characterization and associated EDA tools (Schematic editor, Spice Simulators, Characterization Infrastructure etc.).
Please send your application (preferably by e-mail) with CV and certificates to: hr.kch@xfab.com
Contact person: Sandie Jane Ak James Patrick Uding or online at: Sandie.Uding(at)xfab.com
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