Job Description

Lattice Overview

Lattice is the source for innovative FPGA, PLD, and programmable Power Management solutions. We design and develop programmable logic solutions, which allow the end customer to determine functionality. Our customers are primarily original equipment manufacturers in the communications, computing, consumer, industrial, automotive, medical and military end markets.

Not only does Lattice offer unparalleled product portfolios in a very competitive industry, but it also offers a fantastic working environment that allows the employee\xe2\x80\x99s unique individuality to flourish. Lattice is a mid-size company with a small-size mentality where each employee has the opportunity to make a direct impact on the company\xe2\x80\x99s successes.

Lattice is seeking a Senior CAD Senior Engineer that is experienced in VLSI design & EDA, to join our CAD Engineering group in Penang, Malaysia. Qualified candidates must be either BSEE/CE, or MSEE students and with 10 to 15 years of industry experience on advanced process technology node. This individual will be the key driver to develop and support the custom design methodology & flow.

Responsibilities & Skills

Accountabilities

• Develop and support CDC, linting and logic verification methodology & flow automation within Lattice\xe2\x80\x99s unique EDA design platform for advanced FPGA design
• Analyse and identify solution for tool limitation to enable project productivity continue while pending patches from vendor
• Drive cross functional initiatives & methodologies with a focus on productivity and continuous improvement
• Create, release, and maintain standard design scripts to automate EDA tools & flows
• Tracking and resolution of tool and technology file issues with hands-on management of Foundry and EDA vendor support teams
• Define and implement comprehensive design QA procedures and test suites
• Document and delivery training on developed methodology and EDA flows
• Monitor EDA industry trends and new capabilities by attending conferences and research forums

• BSEE/CE, or MSEE with at least 10 to 15 years of industry EDA experience including logic verification experience
• Knowledge in CDC, linting, and logic verification concepts and must demonstrates superior critical thinking skills, problem solving capabilities and engineering judgement
• Fluent in Verilog RTL and familiar with testbench
• Experience with setting up, documenting, and maintaining EDA tools such as Cadence Xcelium, Cadence Jasper Gold, Synopsys Spyglass, Synopsys VCS, Siemen Questa
• Strong understanding in GLS simulation and testbench
• Detailed understanding on Verilog syntax and RTL styles

• Medical (HMO), dental, vision effective on date of hire
• Employee Stock Purchase Plan, Well-being Programs, Tuition Reimbursement and more

Lattice Semiconductor