Job Description

Lattice Overview

There is energy here\xe2\x80\xa6energy you can feel crackling at any of our international locations. It\xe2\x80\x99s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a \xe2\x80\x9cteam first\xe2\x80\x9d organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you\xe2\x80\x99re looking for.

Responsibilities & Skills

Lattice is seeking a highly motivated individual to join the Global Operations and Quality (GOQ) group as Senior Staff DFT/Diagnosis Engineer. Individual will be responsible for building FPGA patterns consuming SCAN / ATPG vectors or BIST style FPGA design, depending on embedded IP. Pattern will be highly diagnosable using inherent FPGA flexibility. Patterns must be robust enough for manufacturing test running on ATE. Successful Candidate is very familiar with FPGA design flow from Synthesis to Timing Closure. Has had prior experience with FPGA designs. Familiarity with DDR interface and SERDES in FPGA is an absolute plus.

Responsibilities:

• Provide sub-system and/or SOC DFT requirements for RTL/Logic designers, floorplan & PD engineers
• Perform sub-system and/or SOC DFT insertion including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, ATPG
• Simulate ATPG patterns and debug SDF simulation issues
• Verify DFT circuitry and interface with other blocks
• Work closely with physical design team to generate and validate timing SDC
• Be able to quickly understand problem statements and provide innovate solutions for DFT, diagnosis and yield learning
• Be able to work independently and own the complete task from DFT specification to final pattern delivery for sub-system and/or SOC
• Work closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals
• Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test content development

• MSEE or equivalent experience
• 12 years of hands-on experience with DFT and test flow with commercial EDA tools; or 8 years and Master\'s degree
• Working knowledge of TCL, python (or another scripting language like Perl)
• Exceptional written and oral and interpersonal skills with the curiosity to work on rare challenges
• Strong collaborative and interpersonal skills, specifically a proven ability to effectively guide and influence within a dynamic matrix environment

Lattice Semiconductor