Job Description

Lattice Overview

Lattice Semiconductor (NASDAQ: LSCC) is the global leader in smart connectivity solutions, providing market leading intellectual property and low-power, small form-factor devices that enable more than 8,000 global customers to quickly deliver innovative and differentiated cost and power efficient products.

The Company\'s broad, end-market exposure solves customer problems across the network from the Edge to the Cloud for clients in consumer electronics, industrial equipment, communications infrastructure, computing and automotive. Our technology, long-standing relationships and commitment to world-class support enables our customers to quickly and easily unleash innovative solutions to create a smart, secure and connected world.

Our control, connect and compute solutions enable the Internet of Things to operate safely, easily and more autonomously at the edge of the network core. While you may not see our products, you are interacting with them all day, every day. We make your experience smarter and better-connected. Join Team Lattice\xe2\x80\xa6and help us continue to drive innovation that creates a smarter, better-connected world. Together, we enable what\xe2\x80\x99s next.

Responsibilities & Skills

Understand details of High Efficiency FPGA Architecture, standard peripherals such as SPI, I2C, UART, Timer, DMA, memory management schemes, low power spec, multi-processor systems, DDR, PCIe, DDR, Memory Controller Sub Systems, USB, PLL, power up, Secured Boot schemes. Create coverage driven verification plans from specifications, review and refine to achieve coverage targets. Create IP level module and sub-system verification plan, TB, portable test benches, sequences, test infrastructure. Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites to SOC level, achieve targeted coverage, work with design, architecture, SW, FW, and external IP delivery teams to efficiently integrate and verify overall FPGA design.

Key Qualifications:

• 12+ years of dedicated/hands-on FPGA/SOC ASIC DV experience
• Proven track record of working full ASIC verification from concept to tape-out to silicon bring-up
• Advanced knowledge of System Verilog and UVM methodology
• Experience in using programming languages such as C/C++, Perl/Python/Tcl for automatic the DV tasks
• Experience in verifying Subsystems like PCIE (Gen1/2/3/4/5), Ethernet (1G/10G/25G/40G/100G), DDR(2/3/4/5) etc.
• Hands-on verification experience Bus Fabric, AHB, AXI, based bus architecture in UVM environment
• In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification
• Should be a great team leader with excellent communication and problem-solving skills and the desire to seek diverse challenges\xe2\x80\xa2 BS or MS Electrical/Computer Engineering, Computer Science, or related field of study

• Medical (HMO), dental, vision effective on date of hire
• Well-being Programs, Tuition Reimbursement and more

Lattice Semiconductor