Senior Staff Engineer, Ip Design
Pulau Pinang, Malaysia
Job Description
Lattice Overview
We are seeking a Staff IP Design Engineer, passionate individual with technical leadership capabilities to build Connectivity IP portfolios for Lattice FPGA. The individual should have the ability to work closely with architect to translate specifications into high-speed RTL design, for the best Performance, Power and logic utilization.
Responsibilities & Skills
Key Skills
- Experience in high speed DDR protocols is a must.
- Hands-on experience in FPGA RTL design, logic verification, debug and timing closure are essential
- Programming skills (e.g.: C/C++, Perl, TCL or Python).
- Experience in hardware validation or hardware interoperability test is a plus.
- Experience in soft IP packaging, example design and testbench development will be an added advantage.
- BS/MS/PhD in Electronics or Computer Engineering minimum of 10-15 years of FPGA high speed connectivity IP design experience.
- Independent and self-motivated, capable of executing under dynamic environment and uncertainties
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Job Detail
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Job IdJD985473
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IndustryNot mentioned
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Total Positions1
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Job Type:Full Time
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Salary:Not mentioned
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Employment StatusPermanent
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Job LocationPulau Pinang, Malaysia
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EducationNot mentioned