Part of company Back-end Advanced Package Development Team.
Responsible towards package design, Signal and Power Integrity simulation, design verification for various company products (Microcontroller, Memory, Power Devices, ASIC, RF, Sensor, etc).
Perform/Lead Package and PCB electrical model extraction (RLC, PDN), voltage and timing simulation for signal and power integrity analysis using industry standard Engineering Tools.
Work/Lead as a team across functionals with signal integrity centric for customer design adoption support activities.
JOB REQUIREMENTS:
PhD/Master/Bachelor Degree in Electrical, Electronics, Mechatronics,
Optoelectronics, Power, Computer, Telecommunication, System, Software, Physic, Material, Mathematics, or relevant. * Minimum 5 years semiconductor package development experience in design and/or simulation.
Good knowledge in Transmission Line and Electromagnetic theory, D0C/AC signalling concept in time and frequency domain analysis.
Extensive usage of Scattering Parameters for high-speed signals and power delivery network design concept and implementation is a plus.
Hands on capability using Design and/or Simulation Tools (Cadence, ANSYS, Mentor, AutoCAD, ADS, Spice, or any relevant).
Added advantage with experience working on IBIS model, Package/PCB level model extraction, full system voltage and timing simulation, lab measurements.
Good analytical skills on signal integrity analysis (Eye Diagram, Jitter, power noise, signal crosstalk, ringing, lossy attenuation, overshoot/undershoot, etc).
Knowledge in high-speed interface signal integrity design guidelines (LPDDR, PCIE, MIPI, USB, FPD Link, etc).
Encourage extensive lab experience and inspire to venture into simulation hands- on or vice versa.
Reference Number:Contact Details:Siti_Roslan@persolkelly.comProfession:Engineering and Technical Manufacturing & IndustrialCompany:PERSOLKELLY MalaysiaDate Posted:17/05/2024 11:34:00 AM