Job Description

Design Verification Architect
In this position, you will be participating in the leading-edge System-On-a-Chip (SoC) design and verification. You also will be responsible for driving new SOC methodologies which will benefit company processes and technologies. Job Responsibilities

• Understand details of High-Efficiency SOC Architecture, standard SOC peripherals such as SPI,

I2C, UART, Timer, DMA, memory management schemes, low power spec, multi-processor systems, DDR, PCIe, DDR, Memory Controller Sub Systems, USB, PLL, power up, Secured Boot schemes.

• Create coverage driven verification plans from specifications, review and refine to achieve coverage

targets.

• Create IP level module and sub-system verification plan, TB, portable test benches, sequences, test

infrastructure.

• Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-

system test benches and test suites to SOC level, achieve targeted coverage, work with design, architecture, SW, FW and external IP delivery teams to efficiently integrate and verify overall SOC design.

• Contribute to module architecture and block level specification by working with Chip architect
• Work closely with DV methodology architects to improve verification flow.

Qualifications

• Possess a Bachelor\'s, a Master\'s degree or a Ph.D. in Electronics Engineering, Computer

Engineering, or equivalent with at least 8 years of of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog.

• Must have worked with product development teams and the designs must be realized in Silicon

(ASIC tapeouts, *not* FPGA)

• Experience with participating in Post Silicon issue debug is a definite plus
• Hands-on experience with developing timing constraints and running state-of-the-art Synthesis and

Static timing analysis tools

• Good verbal and written communication skills to work effectively with teams spread geographically
• Ability to technically mentor a few junior engineers
• Ability to handle ambiguity, and working cross functional domains across internal and external

teams Strong interest in one or more of the latest methodology areas

• Familiarity with one or more industry-standard bus interfaces and protocols (for example, USB, PCI

Express, SATA, AMBA, and others)

• Good Knowledge of Processor/SoC architecture, DSP fundamentals with Deep knowledge of key

protocols and architectures \xe2\x80\x93 AXI/ARM/RISC-V

• Experience with Lint, CDC, formal equivalence, ECO flows and scripting
• Solid understanding in the latest SOC methodology in DV, Design-for-verification, Machine

Learning, HW/SW co-verification as example

• Design-for-verification (DFV) methodology to improve verification of chipset / multicore
• Application of Machine Learning/ Artificial Intelligence in SOC design and flows across all

functions

• SOC design and bridge the gap between verification, emulation and bring up/validation
• Shift left methodology HW/SW/FW co-verification/emulation Methodology

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