Staff/Principal Design Verification Engineer : As a Design Verification Engineer, you will be working on:
Defines and implements verification procedures for IP Hardware product based on features,
requirements, and failure points.
Creates initial product verification methodology, selecting the verification strategy, identify
failure points and developing test plans.
Develops verification environments and collaterals such as testbenches, stimulus/sequences,
checkers, assertions, and coverage.
Performs tests regression, collects and analyzes regression results, root-causes and resolves
regression failures.
Provides technical direction, guidance and support to the IP development team and stakeholders
throughout the Product Life Cycle.
Influences on product development execution efficiency and quality through continuous
improvement on verification methodologies and strategies used across product families. Minimum Qualifications: Possess a Bachelor\'s, a Master\'s degree or a Ph.D. in Electronics Engineering, Computer Engineering, or equivalent and experience with IP/SoC design or verification development.
At least 8 years of relevant working experience in Silicon Logic Design or verification
development.
Strong technical leader who communicates well with great influencing skills.
Strong analysis, debugging skills, and creative in problem solving.
Motivated, Self-driven and Independent
Additional Qualifications: Experience in any of these design tools and methodologies:
System Verilog (OVM/UVM)
Scripting (Python/Perl/Shell)
RTL simulators
Interactive debugger
RTL model build
Testbench development
Power-aware simulation
Coverage-based random constraint simulation
Formal Property Verification
Experience in any of these areas:
Power Management
Design For Test/Verification (DFT/DFV/DFX)
USB, PCI-Express specifications
Any industry standard device OR interface protocol
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