Job Description

Lattice Overview

There is energy here\xe2\x80\xa6energy you can feel crackling at any of our international locations. It\xe2\x80\x99s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a \xe2\x80\x9cteam first\xe2\x80\x9d organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you\xe2\x80\x99re looking for.

Responsibilities & Skills

Lattice is seeking a highly motivated individual to join the Global Operations and Quality (GOQ) group as Diagnosis Engineer. Individual will be responsible for building FPGA patterns consuming SCAN / ATPG vectors or BIST style FPGA design, depending on embedded IP. Pattern will be highly diagnosable using inherent FPGA flexibility. Patterns must be robust enough for manufacturing test running on ATE. Successful Candidate is very familiar with FPGA design flow from Synthesis to Timing Closure. Has had prior experience with FPGA designs. Familiarity with DDR interface and SERDES in FPGA is an absolute plus.

Primary Responsibilities

• Review with Front End DFT engineer the SCAN / ATPG content and have a scheme for FPGA level integration (Multi-Instance designs with parallelism and diagnosibility)
• Propose or consult with Design Expert BIST algorithm to functionally test the embedded IP. IPs could as simple as Block RAMs or as complicated at SERDES or DDRs.
• Work with Coverage Expert to improve the Test content to achieve desirable coverage goal.
• Release patterns to ATE and resolve any sensitivities to assure robust pattern during manufacturing test.
• Work with Diagnosis / FA engineer to debug & diagnose Failing cases for the purpose of Yield Improvement or customer issue.

• BS or MS degree in Electrical Engineering or equivalent with a minimum of 2 years experience in FPGA design (Using FPGA)
• Very comfortable with RTL (Verilog) design flow from Synthesis to Place & Route
• Experience with either FPGA Vendor tools is a MUST. Knowing Lattice\'s Tool flow is desired.
• Debug and Diagnosis skill for FPGA patterns is assumed
• Ability to script using Perl or Python and TCL coding
• Is knowledgable of Diagnosis methods to electrically isolate failures on silicon.
• Can clearly communicate with Design, Yield teams on SCAN / ATPG failures and lead the effort to debug.

• Medical (HMO), dental, vision effective on date of hire
• Well-being Programs, Tuition Reimbursement and more

Lattice Semiconductor