Job Description

Lattice Overview

Lattice Semiconductor (NASDAQ: LSCC) is the global leader in smart connectivity solutions, providing market leading intellectual property and low-power, small form-factor devices that enable more than 8,000 global customers to quickly deliver innovative and differentiated cost and power efficient products.

The Company\'s broad, end-market exposure solves customer problems across the network from the Edge to the Cloud for clients in consumer electronics, industrial equipment, communications infrastructure, computing and automotive. Our technology, long-standing relationships and commitment to world-class support enables our customers to quickly and easily unleash innovative solutions to create a smart, secure and connected world.

Our control, connect and compute solutions enable the Internet of Things to operate safely, easily and more autonomously at the edge of the network core. While you may not see our products, you are interacting with them all day, every day. We make your experience smarter and better-connected. Join Team Lattice\xe2\x80\xa6and help us continue to drive innovation that creates a smarter, better-connected world. Together, we enable what\xe2\x80\x99s next.

Responsibilities & Skills

Lattice is seeking a highly motivated individual to join the Global Operations and Quality (GOQ) group as SCAN / ATPG DFx / Diagnosis Engineer. Individual will be responsible from design phase of DFT till release of ATPG vectors and FPGA pattern generation to Production. Successful Candidate is very familiar with industry standard DFT methodology. Has experience in verifying DFT solutions in complex SOC. Has implemented RTL code in FPGA and resolved any sensitivity issues during silicon bring-up. Emphasis will be in building High Coverage, diagnosable FPGA patterns for Embedded IP in FPGA.
Primary Responsibilities

• Review DFx features to ensure high Stuck-At & Transition ATPG coverage
• Review DFx features to ensure a final FPGA implementable, robust & diagnosible manufacturing pattern.
• Work with Verification / Design teams to own the Pre-Tapeout DFx verification of the embedded IP.
• Use Lattice FPGA tools (Radiant) to build a FPGA design to accept ATPG vectors for Multi-instance embedded IPs.
• Verify the design on silicon. Ensure FPGA pattern robustness across Voltage & Temperature in volume production.

• BS or MS degree in Electrical Engineering or equivalent with a minimum of 8+ years\xe2\x80\x99 experience in SOC DFT (SCAN / ATPG) methodology and DFT verification
• 4-5 years of experience in developing robust FPGA patterns. Demonstrated results on Silicon
• High proficiency knowledge of SOC design flow, verification and RTL coding for FPGA
• Debug and Diagnosis skill for FPGA patterns is assumed
• Ability to script using Perl or Python and TCL coding
• Is knowledgable of Diagnosis methods to electrically isolate failures on silicon.
• Can clearly communicate with Design, Yield teams on SCAN / ATPG failures and lead the effort to debug.

• Medical (HMO), dental, vision effective on date of hire
• Well-being Programs, Tuition Reimbursement and more

Lattice Semiconductor