Job Description

This position is within the Design Enablement (DE) organization of Intel Technology Development group. We are looking for a talented individual to build and develop an ASIC testchip team to perform all aspects of the ASIC Design and Signoff flow, including RTL coding, logic validation, GLS, Synthesis, Place and Route, LEC, Quality, Timing, RV, LV and Power. This technical managerial role requires the individual with IP design, validation, implementation and sign off methodology/flows knowledge, and a strong passion to mentor and develop the team to deliver world class result. In this managerial role, responsibilities include although not limited to: - Manage a team of design engineers responsible for logic design/integration, validation, RTL to GDS activities and signoff. - Plan, allocate resources, assign tasks and direct activities of the team to meet aggressive schedules and achieve milestone criteria. - Identify and analyze progress gating issues and implement plans, tasks, and solutions to quickly resolve. - Propose creative, innovative methodology and process initiatives to consistently improve efficiency and quality of deliverables. - Provide coaching, guidance and feedback to direct reports on career development, performance, and productivity issues. - Build a strong and technically vital organization. Cultivate and reinforce appropriate group values, norms and behaviors. #designenablement

Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Bachelor Degree (Masters Degree preferred) in Electrical Engineering, Computer Engineering, Computer Science, or other related field of study 10+ years of relevant experience in silicon design and/or TFM development 5+ years of proven experience in managing teams with a strong record of delivery. Experience in tracking and reporting project progress. Experience in the following areas: - Use of industry standard placement and routing CAD tools - Block floor planning, RTL to gate level netlist generation through synthesis, DFT insertion. placement, clock tree synthesis and route flows, power and static timing analysis and closure, validation of physical design including timing, electrical rules, DRC/LVS, noise, RV checks, formal equivalence verification. - Having knowledge in logic coding/integration is added advantage. - Successfully led one or more design tape-outs using advanced foundry nodes. - Able to provide technical guidance and support to team members throughout the project cycle. - Excellent verbal communication, technical presentation and leadership skills. Self-motivated and well organized. #designenablement

Inside this Business Group

As the world\'s largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore\xe2\x80\x99s Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
JobType Hybrid