Physical Implementation Engineer (senior/ Technical Leader)
Pulau Pinang, Malaysia
Job Description
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General responsibilities:
- Develop and own partition or fullchip physical design implementation of multi-hierarchy low-power designs including floorplan, clock tree synthesis, place and route.
- Conduct STA and timing closure for partition or fullchip.
- Runs and checks IR Drop, EM, and completes PV in advanced technology nodes.
- Collaborate with front-end digital RTL & IP engineers to improve design performance and timing closure.
- Knowledge in multi-VT power grid planning.
- Experience in floorplan creation & analysis.
- Knowledge in CTS and tweaking for optimum clocking structure.
- Running hierarchical, partition or fullchip APR.
- understanding of partition, block level and fullchip PnR methodology.
\xc2\xb7 Scripting in any language, ie. Perl, Tcl, shell.
\xc2\xb7 STA and timing closure.
Pre-requisite:
v BS/MS/PhD in Electronics or Computer Engineering.
v Independent, self-motivated & willing to learn and pick up new skills.
v Experience in advanced nodes from TSMC/GF.
Sub Specialization : Engineering;Electrical / Electronics / Semi-conductor
Type of Employment : Permanent
Minimum Experience : 5 Years
Work Location : Penang
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Job Detail
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Job IdJD971229
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IndustryNot mentioned
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Total Positions1
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Job Type:Full Time
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Salary:Not mentioned
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Employment StatusPermanent
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Job LocationPulau Pinang, Malaysia
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EducationNot mentioned