Physical Implementation Engineer (senior/ Technical Leader)
Job Description
General responsibilities: Develop and own partition or fullchip physical design implementation of multi-hierarchy low-power designs including floorplan, clock tree synthesis, place and route. Conduct STA and timing closure for partition or fullchip. Runs and checks IR Drop, EM, and completes PV in advanced technology nodes. Collaborate with front-end digital RTL & IP engineers to improve design performance and timing closure. Experience & skills: Knowledge in multi-VT power grid planning. Experience in floorplan creation & analysis. Knowledge in CTS and tweaking for optimum clocking structure. Running hierarchical, partition or fullchip APR. understanding of partition, block level and fullchip PnR methodology. Nice-to-have: . Scripting in any language, ie. Perl, Tcl, shell. . STA and timing closure. Pre-requisite: v BS/MS/PhD in Electronics or Computer Engineering. v Independent, self-motivated & willing to learn and pick up new skills. v Experience in advanced nodes from TSMC/GF.
foundit
MNCJobz.com will not be responsible for any payment made to a third-party. All Terms of Use are applicable.
Related Jobs
Job Detail
-
Job IdJD973059
-
IndustryNot mentioned
-
Total Positions1
-
Job Type:Full Time
-
Salary:Not mentioned
-
Employment StatusPermanent
-
Job LocationPulau Pinang, Malaysia
-
EducationNot mentioned