Senior Engineer I - Analog Design
Salary: RM12,000
:
We are seeking an individual with mixed signal design or verification experience to expand this group and build advanced high-speed SERDES and PHY designs in FinFET technologies. A candidate in this position is expected to take the lead, drive issue resolution, recommend and implement Industry best practices for Front End Verification as well as develop Tools, Flows and Methodologies required to make the team a Center of Excellence.
Responsibilities:
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