Job Description

Experience: 6-8 Years Education: B.Tech/B.E. - Any Specialization, Electronics/Telecommunication, Electrical) OR (PG - M.Tech/M.E - Any Specialization, Electrical, Electronics/Telecommunication) Job Location: Penang - Malaysia Responsibilities: Include all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out. Should be able to interface with Front End Design team to resolve Design Issues Mentoring new team member Desired Skills Job Requirement: * Must possess 4+ years of hands on experience, P&R from Netlist to GDS including timing closure and Physical verification. * Design experience in all aspects of physical design. * Low power design implementation is must, using UPF/CPF * Proficient in CADNECE / SYNOPSYS Tool suite * Experience with Mentor Olympus tool is a Plus * Technologies: 10nm, 14nm , 16nm, 20nm and lower nodes * Experience in Mentor caliber tools to run Physical verification * Knowledge of I/R drop analysis is a Plus , using REDHAWK * Experience in Tcl/Tk, PERL is a Plus * Excellent verbal and written communication skills are required. * Excellent interpersonal and analytical skills with the ability to work independently and lead the team. * Highly motivated, excellent team spirit, product and customer oriented.

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