In this position, your scope of responsibilities would include but not limited to the following:
Establish close partnership with Product Engineers to provide solutions on suspected test issue among the list of identified fallout pareto that result in lower than expected CWATY/CWASY yield.
Support Product Engineers to debug the test fallout reported and narrow down whether it is valid device or test robustness issue.
Support Product Engineers in debug the unresolved units of interest on cost projects and provide guidance on disposition direction.
Establish close partnership with Design-For-Test (DFT) engineers to deliver solutions for existing structural test (SCAN, LBIST) optimization and/or coverage improvement.
Support quality team in develop the containment test for confirmed test coverage customer quality complaint (CQC) and enable the manufacturable solution to production per committed timeline to customer.
Support Product Engineers in enable the quality look across test solution that require test/pattern development.
Functional test pattern generation through various environment (SOC test bench, mailbox etc.) for quality containment and look across test development work.
Ability to lead or drive a group of technical team members for fanout of best test practice to applicable products within the technology.
Specific Knowledge/Skills
To ensure your successful performance in this role, your education qualification/working experience should reflect:
Bachelors degree in Electrical & Electronics, Computer Science or equivalent.
Minimum 2 years of relevant working experience, preferably in Semiconductor industry.