Job Description

Professional Type
Engineering / R&D


Job Code
TW11696-016


Position
Memory Design Engineer (Schematic and Characteriza


Company Nationality



Working Location
Malaysia


Academic Background
Master


English Proficiency
Business Level


Qualification
Qualification: Master or higher in Electronics Engineering.
Minimum 5 years of working experience in memory schematic design and characterization. Exposure to complete design cycle of SRAM/ROM memory development
Behavioral Competencies
Good communication skills \xe2\x80\x93 good level in English, written and spoken.
Teamwork and collaboration skills, working within multi-national, multi-site team
Open, curious in new design implementation, integrity and friendly when engaging internal/external customers.
Self-motivated, progressive attitude, and able to work independently with minimum supervision
Excellent writing and reporting skills with strong communication and analytical skills
Able to learn quickly, self-driven and results-oriented
Technical/ Functional Competencies
Experience in using EDA tools for schematic entry and advanced transistor level simulators. Proven experience on transistor-level circuit design and circuit behavior analysis
Solid understanding o



We are looking for a Memory Design Engineer to contribute to a highly innovative team by designing and developing high quality SRAM and ROM. You will work with other team members on the new process design challenges. You will have the chance to create novel low power and high-performance circuits and develop in-house design and verification flows for SRAM and ROM design in the context of ISO26262.
Architecture definition and schematic design of RAM and ROM compilers to get the most optimal circuit in terms of power and performance.
Verification of leafcells/circuit blocks including analysis of circuit behavior, timing marginalities, correct description of timing characterization intent on both pre and post layout netlist across the entire PVT space and compiler cut space.
Implement memory characterization flows based on NLDM/NLPM and CCS characterization
Mitigate risks through proactive design analysis
-Generate front-end views (LIB) for memory IP integration in System-