Job Description

Professional Type
Engineering / R&D


Job Code
TW11696-015


Position
Memory Design Engineer(Layout)


Company Nationality



Working Location
Malaysia


Academic Background
Master


English Proficiency
Business Level


Qualification
Qualification: Master or higher in Electronics Engineering.
Minimum 5 years of working experience in Layout design. Exposure to complete design cycle of SRAM and ROM memories development is an advantage.
Behavioral Competencies
Good communication skills \xe2\x80\x93 good level in English, written and spoken.
Teamwork and collaboration skills, working within multi-national, multi-site team
Open, curious in new design implementation, integrity and friendly when engaging internal/external customers.
Self-motivated, progressive attitude, and able to work independently with minimum supervision
Excellent writing and reporting skills with strong communication and analytical skills
Able to learn quickly, self-driven and results-oriented
Technical/ Functional Competencies
Proven experience in using EDA tools for custom layout design and physical verification DRC, LVS
Experience Programming skills e.g. UNIX shell script, Tcl, Phyton, SKILL would be an advantage.
Under



We are looking for a Memory Design Engineer to contribute to a highly innovative team by designing and developing high quality SRAM and ROM. You will work with other team members on the new process design challenges. You will have the chance to create novel low power and high-performance circuits and develop in-house design and verification flows for SRAM and ROM design in the context of ISO26262.
Development of Memory Leafcell design as per the need of SRAM compiler architecture and Specifications.
Stitching of Memory Leafcells to make a toplevel circuit.
Apply layout best practice to get the most optimal performance SRAM and ROM design within the minimal area. Close collaboration with process development team.
Implementation of Design for Manufacturability technics to reach the target of zero-DPPM (Defective Part Per Million), work closely with schematic designers to identify sensitive area
Physical Verification DRC and LVS
Mitigate risks through proactive design